A prior art method of producing a GasAs MESFET is disclosed in Japanese Laid-open Patent Publication No. 60-120574. FIGS. 2(a) to (g) show cross-sectional views of gate electrode production flow of such a method.
In FIG. 2, reference numeral 1 designates a semi-insulating GaAs substrate. An n type GaAs layer 2 is formed in and at a surface of the semi-insulating GaAs substrate 1, for example, by as ion implantation. An SiO.sub.2 pattern 3 is formed at a gate electrode production region on the n type GaAs layer 2. N.sup.+ regions 4 are formed in the semi-insulating GaAs substrate 1 by ion implantation. A photoresist 6 is disposed on the entire surface of the substrate bearing the SiO.sub.2 pattern 3. The SiO.sub.2 pattern 3 is removed to expose region 2 and separate the photoresist into two regions. A metal 8 and 8a is disposed on and between the photoresist regions. The metal 8 forms a Schottky junction with the n type GaAs layer 2. Reference numeral 9 designates a gate electrode that is left when the excess metal 8 is removed by a lift-off technique.
The production flow will be described.
First of all, n type GaAs layer 2 is produced in a surface region of semi-insulating GaAs substrate 1, for example, by as ion implantation, and SiO.sub.2 pattern 3 is deposited at the gate electrode production region on the n type GaAs layer 2 (FIG. 2(a)). Next, N.sup.+ regions 4 are produced in the semi-insulating GaAs substrate 1 by ion implantation, and are activated by annealing (FIG. 2(b)). Next, photoresist 6 is applied on the entire surface of the substrate bearing the SiO.sub.2 pattern 3, to such a thickness that the surface thereof becomes flat (FIG. 2(c)). The photoresist 6 is etched, for example, by reactive ion etching, to gradually thin the photoresist 6 until the top portion of the SiO.sub.2 pattern 3 is exposed (FIG. 2(d)). Thereafter, the SiO.sub.2 pattern 3 is etched and removed using hydrofluoric acid or the like (FIG. 2(e)). Next, a metal which can form a Schottky junction with the n type GaAs layer 2 such as aluminum, or titanium series metal is deposited over the entire surface of the substrate (FIG. 2( f)). Then, the metal 8a lying outside the gate electrode production region is lifted off, together with the photoresist 6, by an organic solvent such as acetone, thereby producing the gate electrode 9 (FIG. 2(g)). Thus, the gate electrode 9 is produced self-aligned with the n.sup.+ regions 4.
In this prior art MESFET, the photoresist 6 is used both in producing the gate electrode 9 and in making the surface thereof flat. The photoresist 6 is apt to deteriorate at the reactive etching step, thereby resulting in difficulty in its removal in the final lift-off process. Furthermore, since the shapes of internal surfaces of the photoresist 6 are uniquely determined by SiO.sub.2 pattern 3, wing-like tips are likely to occur at the both side surfaces of the gate electrode 9 during its production. Furthermore, since the gate electrode 9 is rectangular, no means is available for suppressing the gate resistance such as shortening the gate length. Furthermore, since the top portion of SiO.sub.2 pattern 3 is exposed by thinning the photoresist 6, that SiO.sub.2 exposure is difficult to detect. This means that the margin for process error and process controllability are poor.